1. Field of the Invention
The present invention relates to a semiconductor structure and a fabricating method thereof, and more particularly to both a semiconductor structure and a pixel structure having a multi-layer storage capacitor and a fabricating method for manufacturing the same.
2. Description of Related Art
The thin film transistor (TFT) is often used as a driving element in a display device. Generally, the TFT can be divided into the amorphous silicon TFT and the low temperature poly-silicon (LTPS) TFT. Since the electron mobility of the LTPS-TFT is over 200 cm2/V-sec, the LTPS-TFT can be fabricated in smaller size and thereby increasing the aperture ratio. Therefore, the brightness of the display device is thus increased and the power consumption is reduced. In addition, a storage capacitor for storing data voltage is also fabricated during the fabricating process of the TFT, so as to improve the display quality.
FIGS. 1A-1F are schematic cross-sectional views illustrating a conventional fabricating process of a pixel structure having an LTPS-TFT and a storage capacitor. Referring to FIG. 1A, a substrate 110 is provided. Poly-silicon layers 122 and 124 are formed in an active element area 112 and in a storage capacitor area 114 of the substrate 110 respectively. In this step, a first photomask (not illustrated) is applied to perform patterning process and thereby obtaining the poly-silicon layers 122 and 124.
Afterwards, referring to FIG. 1B, a gate insulating layer 130 is formed on the substrate 110 to cover the poly-silicon layers 122 and 124. A gate 142 and a first electrode 144 are respectively formed over the poly-silicon layers 122 and 124. In this step, a second photomask (not illustrated) is applied to perform patterning process and thereby obtaining the gate 142 and the first electrode 144. Particularly, as shown in FIG. 1B, the gate 142 is utilized as a mask to perform a self-aligned doping process 150 so that a source 122a, a drain 122b are formed in the poly-silicon layer 122, and a channel 122c is between the source 122a and the drain 122b. Furthermore, a lightly doped drain (LDD) area 122d is also formed in the poly-silicon layer 122 to reduce current leakage.
Referring to FIG. 1C, a patterned dielectric layer 160 is formed on the substrate 110. In this step, a third photomask (not illustrated) is utilized to perform patterning process and thereby fabricating a contact window 162 in the patterned dielectric layer 160 so as to expose the source 122a and the drain 122b. 
Then, referring to FIG. 1D, a source/drain conductive line 172 and a second electrode 174 are fabricated on the patterned dielectric layer 160. The source/drain conductive line 172 is filled into the contact window 162 and thus electrically connected to the source 122a and the drain 122b. In this step, a fourth photomask (not illustrated) is applied to perform patterning process and thereby obtaining the source/drain conductive line 172 and the second electrode 174.
Referring to FIG. 1E, a patterned planar layer 180 is formed on the substrate 110. In this step, a fifth photomask (not illustrated) is utilized to perform patterning process and thereby fabricating a contact window 182 in the patterned planar layer 180 so as to expose a portion of the source/drain conductive line 172.
Referring to FIG. 1F, a pixel electrode 190 is formed on the patterned planar layer 180. The pixel electrode 190 is filled into the contact window 182 and thus contacting the source/drain conductive line 172. In this step, a sixth photomask (not illustrated) is utilized to perform patterning process and thereby fabricating a contact window 182 in the patterned planar layer 180. After fabricating processes of FIG. 1A˜1F, a conventional pixel structure 100 is obtained, and six photomasks are required to perform the above fabricating method. Because the photomask is expensive, the cost of the conventional fabricating process is hard to be reduced.
Furthermore, please refer to FIG. 1F, a storage capacitor 195 is disposed in the storage capacitor area 114 of the substrate 110. A first storage capacitor is formed by the poly-silicon layer 124, the gate insulating layer 130 and the first electrode 144. A second storage capacitor is formed by the first electrode 144, the patterned dielectric layer 160 and the second electrode 174. Referring to FIG. 1B again, the poly-silicon layer 124 in the storage capacitor area 114 is covered by the first electrode 144, so the poly-silicon layer 124 cannot be doped during the doping process 150. Consequently, the storage capacitance of a storage capacitor 195 cannot be effectively increased. Hence, display quality of the display device utilizing the pixel structure 100 is poor.